Central Library OPAC University of Rajshahi

Verilog HDL : a guide to digital design synthesis /

Palnitkar, Samir

Verilog HDL : a guide to digital design synthesis / Samir Palnitkar ; Foreword by Prabhu Goel - 2nd ed. - India : Taj Press, 2003 [Impression 2012]. - 490 p. : ill. ; 24 cm.

Include Index.

9788177589184 :


System Analysis and Design--computer architecture
Verilog (Computer hardware description language)

621.392 / PAV 2012