Verilog HDL

Verilog HDL a guide to digital design synthesis Palnitkar, Samir creator Goel, Prabhu text ii India Taj Press 2003 [Impression 2012] 2012 2003 2nd ed. monographic eng 490 p. : ill. ; 24 cm. Samir Palnitkar ; Foreword by Prabhu Goel Include Index. System Analysis and Design computer architecture Verilog (Computer hardware description language) 621.392 PAV 2012 9788177589184 : BD-RjUL 170316 20211209081540.0 66498 eng