Palnitkar, Samir  <br/><br/>
Verilog HDL :   a guide to digital design synthesis / 
Samir Palnitkar ; Foreword by Prabhu Goel 
 - 2nd ed. 
 - India :  Taj Press,  2003 [Impression 2012]. 
 - 490 p. :  ill. ;  24 cm. 
<br/><br/> Include Index. 
<br/><br/><label>ISBN: </label>9788177589184 : 
<br/><br/><label>Subjects--Topical Terms: </label><br/>System Analysis and Design--computer architecture<br/>Verilog (Computer hardware description language)
<br/><br/><label>Dewey Class. No.: </label>621.392  / PAV 2012